While many simulation-based design environments with associated automatic code generation technology support simulation and code generation of floating-point and fixed point algorithms, it is often difficult or impossible to achieve bit-true results between a design model and generated code implementations. A bit-true simulation is one where finite precision fixed-point and/or floating-point operations are modeled precisely, eliminating the need for an additional logic simulation of the final hardware implementation (i.e., code generation) to determine actual system performance and to generate test vectors. Thus, creation of a bit-true simulation may save time and/or money.
Many fixed point-enabled blocks of design environments (e.g., a signal processing blockset's fast Fourier transform (FFT)) allow a user to specify internal scaling and data sizes to match a target computer processor's internal hardware registers, accumulators, and default rounding modes to achieve numeric equivalence in simulation. However, such user specified options may need to be manually set for each block (e.g., which may be time consuming), and may not enable a user to specify all attributes such that identical results may be achieved. Numerical differences may occur because of inexact characterization (e.g., on the part of the simulation) of the target processor's architecture, compiler, compiler settings, operating system, and/or combinations of the aforementioned. Furthermore, not all blocks may expose internal scaling or bit-widths to this level of fidelity, rendering it impossible for some models to achieve bit-true exactness against the execution results of a target processor.